This invention relates to programmable logic array integrated circuit devices (“programmable logic devices” or “PLDs”), and more particularly to interconnection resources for use on programmable logic devices that increase the speed at which those devices can be made to operate.
Programmable logic devices typically include (1) many regions of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic regions. Each logic region is programmable to perform any of several different, relatively simple logic functions. The interconnection resources are programmable to allow the logic regions to work together to perform much more complex logic functions than can be performed by any individual logic region. Examples of known PLDs are shown in Wahlstrom U.S. Pat. No. 3,473,160, Freeman U.S. Pat. No. Re. 34,363, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, and Jefferson et al. U.S. patent application Ser. No. 09/266,235, all which are hereby incorporated by reference herein.
A frequent objective in the design of PLDs is to increase the speed at which the device can be operated. The speeds at which signals can travel through the interconnection resources between logic regions is particularly important to determining device speed. Overall, the interconnection resources must have the general-purpose capability of connecting any logic region to any other logic region. But in addition to this, it can be helpful to find ways to make faster interconnections between nearby logic regions. Many complex logic tasks can be broken down into parts, each of which can be performed by a respective cluster of logic regions. By providing interconnection resources that facilitate the flexible formation of clusters of logic regions with high-speed interconnection capabilities among the logic regions in such clusters, the ability of the PLD to perform various complex logic tasks at high speed is enhanced.
In view of the foregoing, it is an object of this invention to provide improved interconnection resources for programmable logic devices.
It is a more particular object of this invention to provide interconnection resources for programmable logic devices that facilitate the formation of extended clusters of nearby logic modules between which high-speed interconnections can be made.